verilog code for multiple bit input demultiplexer

module demux_2x1(
    input [31:0] a,
    input s,
    output [31:0] y0,y1
    );

genvar i;

for(i =0; i<=31;i=i+1)
begin : fora

assign y0[i] = a[i] & (~s); // this will check for every bit in the input a
assign y1[i] = a[i] & s;

end

endmodule

verilog code for 4 bit ALU Design

`timescale 1ns / 1ps

module alu( a, b, sel, en, y );
input [3:0] a, b;
input  [3:0] sel;
input en;
output reg [7:0] y;
always@(*)
begin
if(en==1)
  begin
case(sel)
4'd0: begin  y = a + b;end
4'd1: begin  y=a-b; end
4'd2:  y=a*b;
4'd3:  y={4'b0, ~a};
4'd4:  y={4'd0, (a & b)};
4'd5:  y={4'd0, (a | b)};
  4'd6: y={4'd0, (a ^ b)};
4'd7: y={4'd0, ~(a & b)};
4'd8: y={4'd0, ~(a | b)};
4'd9: y={4'd0, ~(a ^ b)};
default: begin end
endcase
    end
else
y=8'd0;
end
endmodule

What is 45nm or 16nm or 9nm or nano (nm) meter or micro meter(um) in VLSI?

This is the processes technology based on MOSFET gate length.

Let us consider a simple MOSFET, 

In the above diagram L (length) represents the length of the gate; And W (width) represents the width of the gate. The 180nm or 90nm or 45nm or 16nm or 9nm represents this length. When we say the IC is designed with this technology in the sense actually we are representing the gate length of the transistor used in this IC. All the remaining transistors will also have the same gate length. this also described as the smallest pattern which can be drawn on the surface of the silicon chip.

NOTE: Some of may think that 45nm is the actual IC size but it is not correct it represents the transistor gate length. Even it will not represent the entire transistor size.

Anteena Effect

Antenna effect

Figure 1: Illustration of the cause of antenna effect. M1 and M2 are the first two metals interconnect layers.

The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Fabs normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation. The word antenna is something of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used in this context, but this is less common since there are many effects, and the phrase does not make clear which is meant.

Figure 1(a) shows a side view of a typical net in an integrated circuit. Each net will include at least one driver, which must contain a source or drain diffusion (in newer technology implantation is used), and at least one receiver, which will consist of a gate electrode over a thin gate dielectric (see Figure 2 for a detailed view of a MOS transistor). Since the gate dielectric is so thin, only a few molecules thick, a big worry is breakdown of this layer. This can happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. (Historically, the gate dielectric has been silicon dioxide, so most of the literature refers to gate oxide damage or gate oxide breakdown. As of 2007, some manufacturers are replacing this oxide with various high-κ dielectric materials which may or may not be oxides, but the effect is still the same.)

Figure 2. Diagram of a MOSFET, showing source/drain implant and gate dielectric.

Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide.

However, during the construction of the chip, the oxide may not be protected by a diode. This is shown in figure 1(b), which is the situation while metal 1 is being etched. Since metal 2 is not built yet, there is no diode connected to the gate oxide. So if a charge is added in any way to the metal 1 shape (as shown by the lightning bolt) it can rise to the level of breaking down the gate oxide. In particular, reactive-ion etching of the first metal layer can result in exactly the situation shown - the metal on each net is disconnected from the initial global metal layer, and the plasma etching is still adding charges to each piece of metal.

Leaky gate oxides, although bad for power dissipation, are good for avoiding damage from the antenna effect. A leaky oxide can prevent a charge from building up to the point of causing oxide breakdown. This leads to the somewhat surprising observation that a very thin gate oxide is less likely to be damaged than a thick gate oxide, because as the oxide grows thinner, the leakage goes up exponentially, but the breakdown voltage shrinks only linearly.

Antenna rules

Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is one such ratio for each interconnect layer. The area that is counted may be more than one polygon —it is the total area of all metal connected to gates without being connected to a source/drain implant.

• If the process supports different gate oxides, such as a thick oxide for higher voltages and a thin oxide for high performance, then each oxide will have different rules.
• There are cumulative rules, where the sum (or partial sum) of the ratios over all interconnect layers sets the limit.
• There are rules that consider the periphery of each polygon, as well.

Before signing-off a physical design/layout for fabrication, the Antenna Rule Check is therefore performed.

Fixes for antenna violations

Figure 3: Illustration of three possible fixes to an antenna violation.

In general, antenna violations must be fixed by the router. Possible fixes include:

• Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur. This solution is shown in Figure 3(a).
• Add vias near the gate(s), to connect the gate to the highest layer used. This adds more vias, but involves fewer changes to the rest of the net. This is shown in Figure 3(b).
• Add diode(s) to the net, as shown in Figure 3(c). A diode can be formed away from a MOSFET source/drain, for example, with an n+ implant in a p-substrate or with a p+ implant in an n-well. If the diode is connected to metal near the gate(s), it can protect the gate oxide. This can be done only on nets with violations, or on every gate (in general by putting such diodes in every library cell). The "every cell" solution can fix almost all antenna problems with no need for action by any other tools. However, the extra capacitance of the diode makes the circuit slower and more power hungry.

use of BODY terminal in MOSFET

The body terminal is there whether we like it or not because of the construction of a MOSFET:

The gate voltage modifies the channel width. But the gate potential is measured relative to the substrate potential, and the channel is formed in the substrate material. Therefore the MOSFET behavior depends strongly on the substrate (body) potential.

If we did not make a contact to the body, it would be free to float, and we could not control the behavior of the transistor. We connect to the body to take control of this behavior. Normally we tie the body to either a most-positive or most-negative potential, like you say, because that gives the lowest |V_gs| relative to the appropriate supply and prevents forward biasing the source-body junction. If we did not contact the body, it would still be there, but we would not have control over its effect.

Cadence Virtuoso 6.1.4 creating schematic and layout

Caedence Virtuoso design steps

In order design a project in the Cadence Virtuoso the following steps should be followed.
this post is about the Cadence virtuoso 6.1.14 version.
1. the first step is In Linux open the terminal by clicking the terminal symbol or pressing CTRL+ALT+T simultaneously. will invoke the terminal.

the terminal should look like above.
2. after getting the terminal we have to go to the cadence library.
for this we have to type the following commands

• cd \ 
• cd Cadence/IC614/work
• source env.sh
• virtuoso &
  

after typing the commands now you will get the Cadence window.
the window might be like this

3. next step is in order create a layout or schematic we have to create a library
this can be created by
File ----> New -----> Library

4. next step is create the library name and at set a pat

5. after creating the name and path the library should be appear in your library manager which is situated at the left hand side of the window

you can see that a library is created by my name venkat in library manager.
6. after this we have create the cell view inn order to view and create the Schematics, sc Symbol, Layout....