verilog code for 4 bit ALU Design

`timescale 1ns / 1ps

module alu( a, b, sel, en, y );
input [3:0] a, b;
input  [3:0] sel;
input en;
output reg [7:0] y;
always@(*)
begin
if(en==1)
  begin
case(sel)
4'd0: begin  y = a + b;end
4'd1: begin  y=a-b; end
4'd2:  y=a*b;
4'd3:  y={4'b0, ~a};
4'd4:  y={4'd0, (a & b)};
4'd5:  y={4'd0, (a | b)};
  4'd6: y={4'd0, (a ^ b)};
4'd7: y={4'd0, ~(a & b)};
4'd8: y={4'd0, ~(a | b)};
4'd9: y={4'd0, ~(a ^ b)};
default: begin end
endcase
    end
else
y=8'd0;
end
endmodule