verilog code for multiple bit input demultiplexer

module demux_2x1(
    input [31:0] a,
    input s,
    output [31:0] y0,y1
    );

genvar i;

for(i =0; i<=31;i=i+1)
begin : fora

assign y0[i] = a[i] & (~s); // this will check for every bit in the input a
assign y1[i] = a[i] & s;

end

endmodule